1. Field of the Invention
The present invention relates to programmable controllers and particularly speed-up of programmable controllers using multi-processor technology.
2. Description of the Related Art
So far, as a programmable controller using multi-processor technology, there has been one illustrated in FIG. 10. Referring to FIG. 10, in the programmable controller, a bit processing unit (abbreviated to BPU hereafter) B and a central processing unit (abbreviated to CPU) C share a memory M, an address bus, and a data bus. A program stored in memory M is formed of a combination of instructions of a first class executed by BPU B and instructions of a second class executed by CPU C. BPU B primarily has control right in executing the program and transfers control right to CPU C when a second-class instruction is executed. Then CPU C executes the second-class instruction. The second class of instructions includes skippable instructions that can be skipped if the preceding instruction is a first class instruction and a certain skip condition is met for the operation result of the preceding first-class instruction. When CPU C receives control right together with a second-class instruction, and if the instruction is a skippable instruction, CPU C refers to the operation result of the preceding instruction to judge whether the operation result satisfies the skip condition or not. If CPU C judges that the operation result satisfies the skip condition, and if the next instruction belongs to the first class, then CPU C returns control right to BPU B.
As described above, in such a prior art programmable controller, CPU C always succeeds control right without condition, if the current instruction belongs to the second class. A program consists of various instructions of both first and second classes and generally contains many skippable instructions. Therefore, speed-up of execution has been hampered by transferring control right many times.